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rev: 1.08 12/2000 1/12 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 0328 sj /ts 32k x 8 256kb asynchronous sram 6, 7, 8, 10, 12 ns 3.3 v v dd corner v dd and v ss soj, tsop commercial temp industrial temp features ? fast access time: 6, 7, 8, 10 , 12 ns ? 90/ 7 5/ 65/50/50 ma at max cycle rate ? single 3.3 v 0.3 v power supply ? all inputs and outputs are ttl-compatible ? fully static operation ? industrial temperature option: ?40 to 85c ? package line up sj: 300 mil, 28 -pin soj package ts: 8 mm x 13.4 mm, 28-pin tsop type i package description the gs 7 0328 is a high speed cmos static ram organized as 32,763 words by 8 bits. static design eliminates the need for external clocks or timing strobes. the gs70328 operates on a single 3.3 v power supply, and all inputs and outputs are ttl- compatible. the gs 7 0328 is available in 300 mil, 28-pin soj and 8 x 13.4 mm 2 , 28-pin tsop type-i packages. pin descriptions symbol description a 0 ?a 14 address input dq 1 ?dq 8 data input/output ce chip enable input we write enable input oe output enable input v dd +3.3 v power supply v ss ground nc no connect top view 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 1 dq 2 dq 3 v ss v dd we a 13 a 8 a 9 a 11 oe a 10 ce dq 8 dq 7 dq 6 dq 5 dq 4 28-pin 300 mil 5 6 7 8 9 10 11 12 13 14 28- pin 8 x 13.4 tsop i 1 2 oe a 11 soj 3 4 a 9 a 8 a 13 we v dd a 14 a 12 a 7 a 6 a 5 a 4 a 3 24 23 22 21 20 19 18 17 16 15 28 27 a 10 ce 26 25 dq 8 dq 7 dq 6 dq 5 dq 4 v ss dq 3 dq 2 dq 1 a 0 a 1 a 2 pin configuration
rev: 1.08 12/2000 2/12 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 0328 sj /ts note: x: ?h? or ?l? note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation shall be restricted to recommen ded operating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. truth table ce oe we dq 1 to dq 8 v dd current h x x not selected isb 1 , isb 2 l l h read i dd l x l write l h h high z absolute maximum ratings parameter symbol rating unit supply voltage v dd ?0.5 to +4.6 v input voltage v in ?0.5 to v dd + 0.5 ( 4.6 v max.) v output voltage v out ?0.5 to v dd + 0.5 ( 4.6 v max.) v allowable power dissipation pd 0.7 w storage temperature t stg ?55 to 150 o c memory array row decoder column decoder address input buffer control i/o buffer a 0 ce we oe dq 1 a 14 block diagram dq 8
rev: 1.08 12/2000 3/12 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 0328 sj /ts notes: 1. input overshoot voltage should be less than v dd +2 v and not exceed 20 ns. 2. input undershoot voltage should be greater than ?2 v and not exceed 20 ns. notes: 1. tested at t a = 25c, f = 1 mhz 2. these parameters are sampled and are not 100% tested. recommended operating conditions parameter symbol minimum typical maximum unit supply voltage for - 7/8/10/12 v dd 3.0 3.3 3.6 v supply voltage for - 6 v dd 3.135 3.3 3.6 v input high voltage v ih 2.0 ? v dd + 0.3 v input low voltage v il ?0.3 ? 0.8 v ambient temperature, commercial range t ac 0 ? 70 o c ambient temperature, industrial range t a i ?40 ? 85 o c capacitance parameter symbol test condition maximum unit input capacitance c in v in = 0 v 5 pf output capacitance c out v out = 0 v 7 pf dc i/o pin characteristics parameter symbol test conditions min max input leakage current i il v in = 0 to v dd ?1ua 1ua output leakage current i lo output high z v out = 0 to v dd ?1ua 1ua output high voltage v oh i oh = ?4 ma 2.4 v ? output low voltage v ol i lo = +4 ma ? 0.4 v
rev: 1.08 12/2000 4/12 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 0328 sj /ts power supply currents ac test conditions parameter symbol test conditions 0 to 70c -40 to 85c 6 ns 7 ns 8 ns 10 ns 12 ns 6 ns 7 ns 8 ns 10 ns 12 ns operating supply current i dd ce v il all other inputs 3 v ih or v il min. cycle time i out = 0 ma 90 ma 75 ma 65 ma 50 ma 50 ma 95 ma 80 ma 70 ma 55 ma 55 ma standby current i sb1 ce 3 v ih all other inputs 3 v ih or v il min. cycle time 45 ma 35 ma 30 ma 25 ma 25 ma 50 ma 40 ma 35 ma 30 ma 30 ma standby current i sb2 ce 3 v dd ? 0.2 v all other inputs 3 v dd ? 0.2 v or 0.2 v 1 ma 2 ma dq vt = 1.4 v 50 w 30pf 1 dq 3.3 v output load 1 output load 2 589 w 434 w 5pf 1 notes: 1. include scope and jig capacitance 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted 3. output load 2 for t lz , t hz , t olz and t ohz parameter conditions input high level v ih = 2.4 v input low level v il = 0.4 v input rise time tr = 1 v/ns input fall time tf = 1 v/ns input reference level 1.4 v output reference level 1.4 v output load fig. 1& 2
rev: 1.08 12/2000 5/12 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 0328 sj /ts ac characteristics * these parameters are sampled and are not 100% tested read cycle parameter symbol -6 -7 -8 -10 -12 unit min max min max min max min max min max read cycle time t rc 6 ? 7 ? 8 ? 10 ? 12 ? ns address access time t aa ? 6 ? 7 ? 8 ? 10 ? 12 ns chip enable access time ( ce ) t ac ? 6 ? 7 ? 8 ? 10 ? 12 ns output enable to output valid ( oe ) t oe ? 3 ? 3.5 ? 4 ? 5 ? 6 ns output hold from address change t oh 2 ? 2 ? 2 ? 2 ? 3 ? ns chip enable to output in low z ( ce ) t lz * 2 ? 2 ? 2 ? 2 ? 3 ? ns output enable to output in low z ( oe ) t olz * 0 ? 0 ? 0 ? 0 ? 0 ? ns chip disable to output in high z ( ce ) t hz * ? 3 ? 3.5 ? 4 ? 5 ? 6 ns output disable to output in high z ( oe ) t ohz * ? 3 ? 3 ? 3.5 ? 4 ? 5 ns
rev: 1.08 12/2000 6/12 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 0328 sj /ts read cycle 1: ce = oe = v il , we = v ih read cycle 2: we = v ih t aa t oh t rc address data out previous data data valid t aa t rc address t ac t lz t oe t olz ce oe data out t hz t ohz d a t a v a l i d high impedance
rev: 1.08 12/2000 7/12 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 0328 sj /ts * these parameters are sampled and are not 100% tested write cycle parameter symbol -6 -7 -8 -10 -12 unit min max min max min max min max min max write cycle time twc 6 ? 7 ? 8 ? 10 ? 12 ? ns address valid to end of write taw 4.5 ? 5 ? 5.5 ? 7 ? 10 ? ns chip enable to end of write tcw 4.5 ? 5 ? 5.5 ? 7 ? 10 ? ns data set up time tdw 3 ? 3.5 ? 4 ? 5 ? 7 ? ns data hold time tdh 0 ? 0 ? 0 ? 0 ? 0 ? ns write pulse width twp 4.5 ? 5 ? 5.5 ? 7 ? 10 ? ns address set up time tas 0 ? 0 ? 0 ? 0 ? 0 ? ns write recovery time ( we ) twr 0 ? 0 ? 0 ? 0 ? 0 ? ns write recovery time ( ce ) twr1 0 ? 0 ? 0 ? 0 ? 0 ? ns output low z from end of write twlz * 2 ? 2 ? 2 ? 2 ? 3 ? ns write to output in high z twhz * ? 3 ? 3 ? 3.5 ? 4 ? 5 ns
rev: 1.08 12/2000 8/12 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 0328 sj /ts write cycle 1: we control write cycle 2: ce control t wc address ce we data in oe data out t aw t cw t as t wp t wr t dw t dh t wlz t whz d a t a v a l i d h i g h i m p e d a n c e t wc address ce ub , lb we data in oe data out t aw t wp t as t cw t wr1 t dw t dh d a t a v a l i d h i g h i m p e d a n c e t b w
rev: 1.08 12/2000 9/12 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 0328 sj /ts 28-pin soj, 300 mil 1 e b1 d a 1 a 2 y e h e q c l g e detail a a b a notes: 1. dimension d& e do not include interlead flash 2. dimension b1 does not include dambar protrusion/intrusion 3. controlling dimension: inches symbol dimension in inch dimension in mm min nom max min nom max a ? ? 0.148 ? ? 3.76 a1 0.025 ? ? 0.64 ? ? a2 0.095 0.100 0.105 2.41 2.54 2.67 b 0.015 ? 0.020 0.38 ? 0.51 b1 0.026 0.028 0.032 0.66 0.71 0.81 c 0.008 0.010 0.012 0.20 0.25 0.30 d 0.705 0.71 0.715 17.91 18.03 18.16 e 0.295 0.300 0.305 7.49 7.62 7.75 e ? 0.05 ? ? 1.27 ? he 0.330 0.335 0.340 8.38 8.51 8.64 ge 0.255 0.265 0.275 6.48 6.73 6.985 l 0.082 ? ? 2.08 ? ? y ? ? 0.004 ? ? 0.10 q 0 o ? 10 o 0 o ? 10 o
rev: 1.08 12/2000 10/12 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 0328 sj /ts 28-pin tsop-i, 8 mm x 13.4 mm 1 e b1 d a 1 a 2 y e h e q c l g e detail a a b a d 1 28 e b q a a 1 a 2 y c detail a e h d l a l1 notes: 1. dimension d& e do not include interlead flash 2. dimension b1 does not include dambar protrusion/intrusion 3. controlling dimension: inches 4. profile tolerance zones for d and e do not include mold protrusion. allowable mold protrusion on e is 0.15 mm per side and on d is 0.25 mm per side. symbol dimension in inch dimension in mm min nom max min nom max a ? ? 0.047 ? ? 1.20 a1 0.002 ? 0.006 0.05 ? 0.15 a2 0.035 0.040 0.041 0.90 1.00 1.05 b 0.007 0.008 0.011 0.17 0.20 0.27 d ? 0.465 ? ? 11.8 ? h d ? .528 ? ? 13.4 ? c 0.004 0.006 0.008 0.10 0.15 0.21 e ? 0.315 ? ? 8.00 ? e ? 0.022 ? ? 0.55 ? l 0.020 0.024 0.028 0.50 0.60 0.70 l1 0.024 0.032 0.040 0.60 0.80 1.00 y ? ? 0.003 ? ? 0.08 q 0 o ? 5 o 0 o ? 5 o
rev: 1.08 12/2000 11/12 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 0328 sj /ts * customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. for example: gs 7 0328 tp-8t ordering information part number * package access time temp. range status gs70328sj-6 300-mil soj 6 ns commercial gs70328sj-7 300-mil soj 7 ns commercial gs70328sj-8 300-mil soj 8 ns commercial gs70328sj-10 300-mil soj 10 ns commercial gs70328sj-12 300-mil soj 12 ns commercial gs70328sj-6i 300-mil soj 6 ns industrial gs70328sj-7i 300-mil soj 7 ns industrial gs70328sj-8i 300-mil soj 8 ns industrial gs70328sj-10i 300-mil soj 10 ns industrial gs70328sj-12i 300-mil soj 12 ns industrial gs70328ts-6 tsop-i 8 x 13.4 mm 2 6 ns commercial gs70328ts-7 tsop-i 8 x 13.4 mm 2 7 ns commercial gs70328ts-8 tsop-i 8 x 13.4 mm 2 8 ns commercial gs70328ts-10 tsop-i 8 x 13.4 mm 2 10 ns commercial gs70328ts-12 tsop-i 8 x 13.4 mm 2 12 ns commercial gs70328ts-6i tsop-i 8 x 13.4 mm 2 6 ns industrial gs70328ts-7i tsop-i 8 x 13.4 mm 2 7 ns industrial gs70328ts-8i tsop-i 8 x 13.4 mm 2 8 ns industrial gs70328ts-10i tsop-i 8 x 13.4 mm 2 10 ns industrial gs70328ts-12i tsop-i 8 x 13.4 mm 2 12 ns industrial
rev: 1.08 12/2000 12/12 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 0328 sj /ts revision history rev. code: old; new types of changes format or content page #/revisions/reason 1.03 8/1999; 1.04 11/1999 content ? added 12ns speed bin information to 70328 datasheet. gs 7 0328 rev 1.0 4 12/1999 krev 1.0 5 2/2000l format/content ? gsi logo rev 1.0 5 2/2000l; rev1.06 6/2000 content ? nominal value for h d on the tsop-i 28-pin package changed to 13.4 rev1.06; rev1.07 format/content ? updated format to conform to tech pubs standards ? corrected errors in both case diagrams 70328_r1_07; 70328_r1_08 content ? added 12 ns reference to parameter column in recommended operating conditions table on page 3

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